1. Field of the Invention
This invention relates to non-volatile semiconductor memory and more specifically to circuits and methods for detecting and correcting data errors in a memory storing multiple bits per memory cell.
2. Description of Related Art
Conventional electrically erasable non-volatile semiconductor memories such as E.sup.2 PROMs and flash memories have memory cells that include transistors with programmable threshold voltages. For example, a floating gate transistor or a split gate transistor has a threshold voltage that is programmed or erased by charging or discharging a floating gate located between a control gate and a channel in the transistor. The amount of charge on the floating gate of the transistor determines the voltage that must be applied to the control gate to cause charge carrier inversion in the underlying channel and therefore determines the threshold voltage of the transistor. Data is written in such memory cells by charging or discharging the floating gates of the memory cells to achieve threshold voltages corresponding to the data.
A binary memory stores one bit of data per memory cell. Accordingly, floating gate transistors in binary memory cells have two distinguishable states, a high threshold voltage state and a low threshold voltage state. Any memory cell having a threshold voltage above a cut-off threshold voltage value is in the high threshold voltage state and stores a bit value, 1 or 0, that corresponds to the high threshold state. Memory cells having threshold voltages below the cut-off are in the low threshold voltage state and store the bit value, 0 or 1, corresponding to the low threshold voltage state.
A multibit-per-cell memory stores multiple bits per memory cell. Accordingly, a range of threshold voltages for a memory cell is divided into a number of states corresponding to the possible multibit data values stored in the memory cell. For example, a memory that stores two bits of data per memory cell has a range of suitable threshold voltages for memory cells that is divided into four states. A first state includes threshold voltages below a first cut-off. A second state includes threshold voltages between the first cut-off and a second cut-off. A third state includes threshold voltages between the second cut-off and a third cut-off, and a fourth state includes threshold voltages above the third cut-off.
A concern in non-volatile semiconductor memory is drift or unintended changes in the threshold voltages of memory cells. For example, over time, charge tends to leak from the floating gates of memory cells and change the threshold voltages of the cells. Charge leakage decreases the threshold voltage of an N-channel memory cell. Alternatively, a floating gate or an insulator surrounding the floating gate can collect or trap charge and increase the threshold voltage of a cell. Further, operation of the memory, for example, programming or reading stresses memory cells not being accessed and can change threshold voltages. Changes in the threshold voltage are a problem because the state of the memory cell and the data value stored in the memory cell can change and create a data error. Such data errors are intolerable in many memory applications. The problem is worse for multibit-per-cell memories than for binary memories because the range of threshold voltages corresponding to a particular state is typically smaller in a multibit-per-cell memory which makes changes in the state of the memory cell more likely.
Multibit-per-cell memories that are resistant to data errors are sought.